An integrated readout circuit for Lab-on-a-Chip applications is presented. The overall system consist of a 640x480 array of capacitor sensors and actuators. Sensors detect dielectric permittivity variation thanks to dielectrophoresis (DEP) process. Usually for this kind of applications an off-chip analog-to-digital converter is used. As a consequence, the noise floor increases and high signal-to-noise ratios are difficulty achieved. On the other hand, these applications requires a stringent noise floor specification (>10b) and a relaxed linearity (approximate to 8b). In this design, the noise coupled to the signal at the chip pad is reduced by using an on-chip analog-to-digital converter. The complete sensor readout channel is composed by two main blocks: a pre-amplifier with programmable gain and an algorithmic analog-to-digital converter with a 1.5-bit/stage architecture. Each one is realized with fully differential switched capacitor technique. In order to save chip area and power consumption a time sharing technique has been taken into account using a single operational amplifier for the pre-amplification stage and the conversion stage. The proposed A/D converter has 11b resolution, a sampling rate of about 100ksample/s and an input full-scale range of 1.2Vp-p differential. Simulation results show a SNR=65.7 dB and an ENOB value of 10.6b. Its power consumption is about 150 mu W. Readout chain is implemented in 0.35 mu m CMOS technology with a 3.3V supply voltage
Delizia, P., D'Amico, S., Baschirotto, A. (2008). A 150µW-11b readout circuit for Lab-on-a-Chip applications. In PRIME: 2008 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS, PROCEEDINGS (pp.193-196). IEEE [10.1109/RME.2008.4595758].
A 150µW-11b readout circuit for Lab-on-a-Chip applications
BASCHIROTTO, ANDREA
2008
Abstract
An integrated readout circuit for Lab-on-a-Chip applications is presented. The overall system consist of a 640x480 array of capacitor sensors and actuators. Sensors detect dielectric permittivity variation thanks to dielectrophoresis (DEP) process. Usually for this kind of applications an off-chip analog-to-digital converter is used. As a consequence, the noise floor increases and high signal-to-noise ratios are difficulty achieved. On the other hand, these applications requires a stringent noise floor specification (>10b) and a relaxed linearity (approximate to 8b). In this design, the noise coupled to the signal at the chip pad is reduced by using an on-chip analog-to-digital converter. The complete sensor readout channel is composed by two main blocks: a pre-amplifier with programmable gain and an algorithmic analog-to-digital converter with a 1.5-bit/stage architecture. Each one is realized with fully differential switched capacitor technique. In order to save chip area and power consumption a time sharing technique has been taken into account using a single operational amplifier for the pre-amplification stage and the conversion stage. The proposed A/D converter has 11b resolution, a sampling rate of about 100ksample/s and an input full-scale range of 1.2Vp-p differential. Simulation results show a SNR=65.7 dB and an ENOB value of 10.6b. Its power consumption is about 150 mu W. Readout chain is implemented in 0.35 mu m CMOS technology with a 3.3V supply voltageI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.


