The paper presents a fully integrated high-voltage 0.35 μm CMOS capacitor-less Low-Dropout (LDO) voltage regulator for car's battery-operated devices in automotive field. The proposed LDO operates between two domains: 3V Vdd and 13.5V Vbat . The load is a One Time Programmable (OTP) antifuse memory, with a dielectric as an antifuse element: once programmed, it becomes conducting. The LDO must be able to constantly power the OTP and program cells, without being sensitive to supply fluctuations and abrupt changes in the load capacitance and resistance. The LDO consists of a single stage high gain opamp and a common source, which works with a 300μA DC current to provide a 10V output. Worst condition simulations over corners and temperatures show robust response while delivering 10mA to a 10pF-variable resistance load. The settling time is less than 1μs at fully load transient. The output voltage error is less than 5% at 6 sigma, minimizing overshoots without involving bulking transient control circuit. The circuit occupies an active area of 0.06 mm 2 .
Gasparri, O., Bozic, A., del Croce, P., Baschirotto, A. (2021). High-Voltage Double-Domain Low-Dropout regulator for rapidly changing output loads. In 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS). 345 E 47TH ST, NEW YORK, NY 10017 USA : Institute of Electrical and Electronics Engineers Inc. [10.1109/ICECS53924.2021.9665584].
High-Voltage Double-Domain Low-Dropout regulator for rapidly changing output loads
Gasparri, O;Baschirotto, A
2021
Abstract
The paper presents a fully integrated high-voltage 0.35 μm CMOS capacitor-less Low-Dropout (LDO) voltage regulator for car's battery-operated devices in automotive field. The proposed LDO operates between two domains: 3V Vdd and 13.5V Vbat . The load is a One Time Programmable (OTP) antifuse memory, with a dielectric as an antifuse element: once programmed, it becomes conducting. The LDO must be able to constantly power the OTP and program cells, without being sensitive to supply fluctuations and abrupt changes in the load capacitance and resistance. The LDO consists of a single stage high gain opamp and a common source, which works with a 300μA DC current to provide a 10V output. Worst condition simulations over corners and temperatures show robust response while delivering 10mA to a 10pF-variable resistance load. The settling time is less than 1μs at fully load transient. The output voltage error is less than 5% at 6 sigma, minimizing overshoots without involving bulking transient control circuit. The circuit occupies an active area of 0.06 mm 2 .File | Dimensione | Formato | |
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