This paper presents a double-domain capacitor-less Low-DropOut (LDO) voltage regulator developed to drive a One Time Programmable (OTP) memory (consisting of 512 memory cells) for circuit trimming in automotive applications. The LDO is powered by the car's battery voltage and generates the OTP programming voltage, regardless of variations on the line and on the load equivalent capacitance and resistance. The LDO steadily provides a 10.8V output with a 0.5% nominal error consuming a 500μ A idle current and it is capable of delivering up to 10mA to a 10pF -variable resistance load. The settling time is <1μs at fully load transient without presenting overshoot and ringing that would cause a faster and uncontrolled deterioration of the cells. An average current of 2.5mA flows in a programmed cell during the programming phase, while 60μA flows during reading phase, making it distinguishable from a virgin cell. In a 0.35μm CMOS technology, the LDO occupies an active area of 220x324μm2 . The measurements validate the proposed structure.
Gasparri, O., Bozic, A., del Croce, P., Baschirotto, A. (2021). A Low-Dropout Regulator for One Time Programmable (OTP) Memories in Automotive Applications. In 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS). Institute of Electrical and Electronics Engineers Inc. [10.1109/ICECS53924.2021.9665607].
A Low-Dropout Regulator for One Time Programmable (OTP) Memories in Automotive Applications
Gasparri, O
;Baschirotto, A
2021
Abstract
This paper presents a double-domain capacitor-less Low-DropOut (LDO) voltage regulator developed to drive a One Time Programmable (OTP) memory (consisting of 512 memory cells) for circuit trimming in automotive applications. The LDO is powered by the car's battery voltage and generates the OTP programming voltage, regardless of variations on the line and on the load equivalent capacitance and resistance. The LDO steadily provides a 10.8V output with a 0.5% nominal error consuming a 500μ A idle current and it is capable of delivering up to 10mA to a 10pF -variable resistance load. The settling time is <1μs at fully load transient without presenting overshoot and ringing that would cause a faster and uncontrolled deterioration of the cells. An average current of 2.5mA flows in a programmed cell during the programming phase, while 60μA flows during reading phase, making it distinguishable from a virgin cell. In a 0.35μm CMOS technology, the LDO occupies an active area of 220x324μm2 . The measurements validate the proposed structure.
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