Wideband amplifiers with low but precisely known dc gain allow the achievement of accurate infinite impulse response switched-capacitor (SC) filters operating at very high sampling frequencies. The low and precise opamp gain value is taken into account while sizing the capacitors (precise opamp gain (POG) approach), so that no idle phase is required for amplitude errors compensation and double-sampling technique can be implemented. In a 0.5-μm standard CMOS technology with 3.3-V power supply, an opamp is designed which exhibits a settling time of about 3 ns (for 0.1% settling accuracy) in a closed-loop configuration with input, feedback, and load capacitors of 0.5 pF, while the slew rate is 1 V/ns. The open-loop dc gain of the amplifier is set to the value of 80 (38 dB) by a gain-control closed loop, which guarantees an accuracy of ±2%. The proposed solution is validated by experimental results from a 200-Ms/s SC filter. From a single 3.3-V supply the filter consumes 10 mW (excluding clock generation) and exhibits a -40 dB total harmonic distortion for a 2-Vpp signal amplitude at 4 MHz, achieving a 62-dB dynamic range.

Baschirotto, A., Severi, F., Castello, R. (2000). 200-Ms/s 10-mW switched-capacitor filter in 0.5-μm CMOS technology. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 35(8), 1215-1219 [10.1109/4.859513].

200-Ms/s 10-mW switched-capacitor filter in 0.5-μm CMOS technology

BASCHIROTTO, ANDREA;
2000

Abstract

Wideband amplifiers with low but precisely known dc gain allow the achievement of accurate infinite impulse response switched-capacitor (SC) filters operating at very high sampling frequencies. The low and precise opamp gain value is taken into account while sizing the capacitors (precise opamp gain (POG) approach), so that no idle phase is required for amplitude errors compensation and double-sampling technique can be implemented. In a 0.5-μm standard CMOS technology with 3.3-V power supply, an opamp is designed which exhibits a settling time of about 3 ns (for 0.1% settling accuracy) in a closed-loop configuration with input, feedback, and load capacitors of 0.5 pF, while the slew rate is 1 V/ns. The open-loop dc gain of the amplifier is set to the value of 80 (38 dB) by a gain-control closed loop, which guarantees an accuracy of ±2%. The proposed solution is validated by experimental results from a 200-Ms/s SC filter. From a single 3.3-V supply the filter consumes 10 mW (excluding clock generation) and exhibits a -40 dB total harmonic distortion for a 2-Vpp signal amplitude at 4 MHz, achieving a 62-dB dynamic range.
Articolo in rivista - Articolo scientifico
Capacitors; Electric distortion; Electric network topology; Electric power supplies to apparatus; Error compensation; Gain control; Harmonic generation; IIR filters; Operational amplifiers; Switched filters;
English
2000
35
8
1215
1219
none
Baschirotto, A., Severi, F., Castello, R. (2000). 200-Ms/s 10-mW switched-capacitor filter in 0.5-μm CMOS technology. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 35(8), 1215-1219 [10.1109/4.859513].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/31166
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