A low power 7.5–10.6 GHz frequency synthesizer for impulse radio ultra-wide band (IR-UWB) is designed and fabricated in 65 nm CMOS technology. The synthesizer is based on an integer-N type-II 4th-order PLL architecture. A 7-bit voltage-controlled oscillator with 31 % tuning range and a set of high-speed dividers are used to synthesize all the carriers defined by the IEEE standard 802.15.4a. The frequency dividers are based on true single phase clock logic resulting in compact implementation and low power consumption. The 0.33 mm2fully integrated synthesizer consumes 5.13 mA from a 1.2 V supply. With a 3-dB closed-loop bandwidth of 100 kHz, the settling time is 15 µs. It features <−103 dBc/Hz measured phase noise at 1 MHz offset. The out-of-band spurious tones result below −59 dBc.
D'Amico, S., Donno, A., Conta, M., Baschirotto, A. (2016). A 6.1 mW 7.5–10.6 GHz PLL-based frequency synthesizer for IEEE 802.15.4a UWB transceivers. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 88(3), 383-389 [10.1007/s10470-016-0758-5].
A 6.1 mW 7.5–10.6 GHz PLL-based frequency synthesizer for IEEE 802.15.4a UWB transceivers
Baschirotto A.
2016
Abstract
A low power 7.5–10.6 GHz frequency synthesizer for impulse radio ultra-wide band (IR-UWB) is designed and fabricated in 65 nm CMOS technology. The synthesizer is based on an integer-N type-II 4th-order PLL architecture. A 7-bit voltage-controlled oscillator with 31 % tuning range and a set of high-speed dividers are used to synthesize all the carriers defined by the IEEE standard 802.15.4a. The frequency dividers are based on true single phase clock logic resulting in compact implementation and low power consumption. The 0.33 mm2fully integrated synthesizer consumes 5.13 mA from a 1.2 V supply. With a 3-dB closed-loop bandwidth of 100 kHz, the settling time is 15 µs. It features <−103 dBc/Hz measured phase noise at 1 MHz offset. The out-of-band spurious tones result below −59 dBc.
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