The high luminosity and interaction rate expected from the planned High Luminosity-Large Hadron Collider (HL-LHC) upgrade require a replacement and improvement of the ATLAS Muon-Drift-Tube (MDT) read-out electronics. This paper presents a Phase Locked Loop (ePLL) intended to be used inside the improved Time-to-Digital Converter (TDC), which digitizes the arrival time and charge amplitude information. Starting from a 40 MHz input clock, the ePLL provides output clocks of 160 MHz and 320 MHz with a phase resolution of 11.25° and 22.5°, respectively. The prototype, integrated in 130 nm CMOS technology, has 0.02 mm2 of area and 1.2V of supply voltage.
Pipino, A., de Matteis, M., Resta, F., Baschirotto, A., Kroha, H., Richter, R., et al. (2018). A 130 nm CMOS PLL for phase-II ATLAS-MDT TDC. In Proceedings of Science. Sissa Medialab Srl.
A 130 nm CMOS PLL for phase-II ATLAS-MDT TDC
Pipino A.
;de Matteis M.;Resta F.;Baschirotto A.;
2018
Abstract
The high luminosity and interaction rate expected from the planned High Luminosity-Large Hadron Collider (HL-LHC) upgrade require a replacement and improvement of the ATLAS Muon-Drift-Tube (MDT) read-out electronics. This paper presents a Phase Locked Loop (ePLL) intended to be used inside the improved Time-to-Digital Converter (TDC), which digitizes the arrival time and charge amplitude information. Starting from a 40 MHz input clock, the ePLL provides output clocks of 160 MHz and 320 MHz with a phase resolution of 11.25° and 22.5°, respectively. The prototype, integrated in 130 nm CMOS technology, has 0.02 mm2 of area and 1.2V of supply voltage.
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