A Fast Tracker analog front end for small-diameter Muon Drift Tube (sMDT) detectors is hereby presented. The analog channel has been integrated in 28 nm CMOS technology and significantly improves state-of-the-art sMDT read-out systems thanks to a novel signal processing technique exploited to extract information from sMDT detectors speeding-up the processing time and to limit fake events detection. The main idea is to implement a fast reset of all continuous-time analog stages that occurs just after the charge (i.e. event) detection. This has two main advantages for sMDT read-out: fast processing and negligible signal corruption due to non-relevant pile-up signals. Nonetheless, the realization in 28nm bulk-CMOS technology implies challenges for analog design but advantages in terms of speed, area occupancy and radiation hardness. The proposed analog channel occupies 0.03 mm2 and consumes 1.9 mW from 1 V supply voltage.
Pipino, A., Resta, F., Mangiagalli, L., Fary, F., De Matteis, M., Kroha, H., et al. (2019). SMDT detectors read-out in 28nm technology. In 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 (pp.691-694). 345 E 47TH ST, NEW YORK, NY 10017 USA : Institute of Electrical and Electronics Engineers Inc. [10.1109/ICECS46596.2019.8964714].
SMDT detectors read-out in 28nm technology
Pipino A.;Resta F.;Mangiagalli L.;Fary F.;De Matteis M.;Baschirotto A.
2019
Abstract
A Fast Tracker analog front end for small-diameter Muon Drift Tube (sMDT) detectors is hereby presented. The analog channel has been integrated in 28 nm CMOS technology and significantly improves state-of-the-art sMDT read-out systems thanks to a novel signal processing technique exploited to extract information from sMDT detectors speeding-up the processing time and to limit fake events detection. The main idea is to implement a fast reset of all continuous-time analog stages that occurs just after the charge (i.e. event) detection. This has two main advantages for sMDT read-out: fast processing and negligible signal corruption due to non-relevant pile-up signals. Nonetheless, the realization in 28nm bulk-CMOS technology implies challenges for analog design but advantages in terms of speed, area occupancy and radiation hardness. The proposed analog channel occupies 0.03 mm2 and consumes 1.9 mW from 1 V supply voltage.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.