A 3rd-order 132MHz cut-off frequency low-pass filter in 28nm CMOS-bulk technology is presented. Challenges related to the design of analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order filter transfer function. The proposed circuit solution enables high linearity (IIP3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340μν without that the Signal-To-Noise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-The-Art.
De Matteis, M., Donno, A., Marinaci, S., D'Amico, S., Baschirotto, A. (2017). A 0.9V 3rd-order single-OPAMP analog filter in 28nm CMOS-bulk. In Proceedings - 2017 7th International Workshop on Advances in Sensors and Interfaces, IWASI 2017 (pp.155-158). Institute of Electrical and Electronics Engineers Inc. [10.1109/IWASI.2017.7974237].
A 0.9V 3rd-order single-OPAMP analog filter in 28nm CMOS-bulk
De Matteis, M;Donno, A;Baschirotto, A
2017
Abstract
A 3rd-order 132MHz cut-off frequency low-pass filter in 28nm CMOS-bulk technology is presented. Challenges related to the design of analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order filter transfer function. The proposed circuit solution enables high linearity (IIP3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340μν without that the Signal-To-Noise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-The-Art.
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