In this paper, the impact of an electrical stress applied on MOS structures with a 9.8-nm-thick SiO2 layer has been investigated at the device level and at the nanoscale with conductive atomic force microscopy (AFM). The goal is to correlate both kinds of measurements when studying the degradation and breakdown (BD) of tunnel oxides of nonvolatile memory devices. In particular, the generation of defects and its impact on leakage current and charge trapping in the tunnel oxide have been analyzed through spectroscopic measurements and current images. The properties and energy of the stress-induced defects (before and after BD) have been roughly estimated by thermally stimulated luminescence and AFM measurements. © 2009 IEEE.
Lanza, M., Porti, M., Nafría, M., Aymerich, X., Sebastiani, A., Ghidini, G., et al. (2009). Combined Nanoscale and Device-Level Degradation Analysis of SiO2 Layers of MOS Nonvolatile Memory Devices. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 9(4), 529-536.
Combined Nanoscale and Device-Level Degradation Analysis of SiO2 Layers of MOS Nonvolatile Memory Devices
VEDDA, ANNA GRAZIELLA;FASOLI, MAURO
2009
Abstract
In this paper, the impact of an electrical stress applied on MOS structures with a 9.8-nm-thick SiO2 layer has been investigated at the device level and at the nanoscale with conductive atomic force microscopy (AFM). The goal is to correlate both kinds of measurements when studying the degradation and breakdown (BD) of tunnel oxides of nonvolatile memory devices. In particular, the generation of defects and its impact on leakage current and charge trapping in the tunnel oxide have been analyzed through spectroscopic measurements and current images. The properties and energy of the stress-induced defects (before and after BD) have been roughly estimated by thermally stimulated luminescence and AFM measurements. © 2009 IEEE.
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