In this paper a complete design of a Content Addressable Memory (CAM) in bulk-CMOS 28nm technology is presented. The CAM has 64×18 bit resolution, operates at 200MHz and exploits the low power pipeline searching algorithm. Dedicated circuital solutions have been adopted to mitigate the well-known issues in CMOS 28nm-bulk technology (like higher sensitivity to Process-Voltage-Temperature variations, increased gate serie resistance, very low supply voltage vs. threshold voltage, etc). This allows to take advantage of the larger transition frequency available in nm-range technologies and the lower parasitic capacitances. Simulation results (based on post-layout extracted schematic) have been carried out, validating this way the hereby proposed CAM design. Overall average power consumption is 153μW, corresponding to 0.65fJ/(Bit·Search), one of the higher Figure-of-Merit comparing with similar CAM architectures available in literature. Total area occupancy for 1.152kb resolution is 0.015mm2.

Fary, F., Mangiagalli, L., Pipino, A., Resta, F., De Matteis, M., Baschirotto, A. (2017). A 200MHz 0.65fJ/(Bit·Search)1.152kb pipeline content addressable memory in 28nm CMOS. In PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings, Taormina, 12-15 June 2017 (pp.353-356). Institute of Electrical and Electronics Engineers Inc. [10.1109/PRIME.2017.7974180].

A 200MHz 0.65fJ/(Bit·Search)1.152kb pipeline content addressable memory in 28nm CMOS

Fary, F
;
Mangiagalli, L;Pipino, A;Resta, F;De Matteis, M;Baschirotto, A.
2017

Abstract

In this paper a complete design of a Content Addressable Memory (CAM) in bulk-CMOS 28nm technology is presented. The CAM has 64×18 bit resolution, operates at 200MHz and exploits the low power pipeline searching algorithm. Dedicated circuital solutions have been adopted to mitigate the well-known issues in CMOS 28nm-bulk technology (like higher sensitivity to Process-Voltage-Temperature variations, increased gate serie resistance, very low supply voltage vs. threshold voltage, etc). This allows to take advantage of the larger transition frequency available in nm-range technologies and the lower parasitic capacitances. Simulation results (based on post-layout extracted schematic) have been carried out, validating this way the hereby proposed CAM design. Overall average power consumption is 153μW, corresponding to 0.65fJ/(Bit·Search), one of the higher Figure-of-Merit comparing with similar CAM architectures available in literature. Total area occupancy for 1.152kb resolution is 0.015mm2.
No
slide + paper
CMOS; Content-Addressable-Memory; Integrated Digital Circuits; Low-Power; Low-Voltage;
CMOS; Content-Addressable-Memory; Integrated Digital Circuits; Low-Power; Low-Voltage; Electrical and Electronic Engineering; Instrumentation
English
13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017
9781509065073
Fary, F., Mangiagalli, L., Pipino, A., Resta, F., De Matteis, M., Baschirotto, A. (2017). A 200MHz 0.65fJ/(Bit·Search)1.152kb pipeline content addressable memory in 28nm CMOS. In PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings, Taormina, 12-15 June 2017 (pp.353-356). Institute of Electrical and Electronics Engineers Inc. [10.1109/PRIME.2017.7974180].
Fary, F; Mangiagalli, L; Pipino, A; Resta, F; De Matteis, M; Baschirotto, A
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/179426
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