This paper presents a continuous-time 3rd order ΣΔ modulator implemented in 40-nm CMOS technology for closing the feedback loop of a digital class-D audio amplifier. The proposed ΣΔ A/D converter consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB DR and 72-dB peak SNDR. The active-RC implementation allows the 1.1-V ΣΔ modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees 3rd order anti-aliasing filtering. © 2013 IEEE
Donida, A., Malcovati, P., Nagari, A., Cellier, R., & Baschirotto, A. (2013). A 40-nm CMOS, 1.1-V, 101-dB DR, 1.7-mW continuous-time ΣΔ ADC for a digital closed-loop class-D amplifier. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (pp.437-440). Institute of Electrical and Electronics Engineers Inc..
Citazione: | Donida, A., Malcovati, P., Nagari, A., Cellier, R., & Baschirotto, A. (2013). A 40-nm CMOS, 1.1-V, 101-dB DR, 1.7-mW continuous-time ΣΔ ADC for a digital closed-loop class-D amplifier. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (pp.437-440). Institute of Electrical and Electronics Engineers Inc.. |
Tipo: | paper |
Carattere della pubblicazione: | Scientifica |
Presenza di un coautore afferente ad Istituzioni straniere: | Si |
Titolo: | A 40-nm CMOS, 1.1-V, 101-dB DR, 1.7-mW continuous-time ΣΔ ADC for a digital closed-loop class-D amplifier |
Autori: | Donida, A; Malcovati, P; Nagari, A; Cellier, R; Baschirotto, A |
Autori: | BASCHIROTTO, ANDREA (Ultimo) |
Data di pubblicazione: | 2013 |
Lingua: | English |
Nome del convegno: | IEEE International Conference on Electronics, Circuits, and Systems december 8-11 |
ISBN: | 978-1-4799-2452-3 |
Appare nelle tipologie: | 02 - Intervento a convegno |