General-purpose processors are optimized for executing complex sequences of instructions for average application workloads. Nevertheless, many algorithms contain critical “kernels” of instructions that significantly impact total application performance, and which are unlikely to be perfectly implemented by any general purpose processor. In this case, a programmable hardware core coupled with a standard processor could significantly improve the application performance; such architectures are called reconfigurable architectures. Of course the system needs to be provided with a programming environment that exploits well the architecture capabilities. In this paper we first describe the state of the art about the automatic compilation flows for reconfigurable architectures; then we illustrate our compilation approach towards automatic optimized compilation that we are developing on the XiRISCPiCoGA architecture.
|Citazione:||Rosti, A., Gallini, A., Ferretti, C., & Bocchio, S. (2006). Compilation Techniques for Configurable Architectures. In ReCoSoC International Workshop 2006, Univ. Montpellier II (pp.38-45).|
|Carattere della pubblicazione:||Scientifica|
|Titolo:||Compilation Techniques for Configurable Architectures|
|Autori:||Rosti, A; Gallini, A; Ferretti, C; Bocchio, S|
|Data di pubblicazione:||2006|
|Nome del convegno:||ReCoSoC International Workshop 2006, Univ. Montpellier II|
|Appare nelle tipologie:||02 - Intervento a convegno|