In this paper, a novel 10-bit A/D converter based on a pipeline-like architecture specific for low-noise, self-triggered sensors, (e.g., X-rays and γ-rays spectrometry) is presented. The main innovative feature of the proposed A/D structure is the concept that, for a sampled input signal, a pipeline ADC may behave as a combinatorial logic and may operate without any timing signal (clock). The conversion is obtained asynchronously propagating the partial conversions and the residues through the various stages. This concept is validated by means of a prototype ADC fabricated in a standard 0.35 μm CMOS technology. The active area is 2.24mm2, and it provides a conversion in 2.5 μs (i.e., it can operate with a 400 kS/s data rate) featuring an ENOB equal to 8.91. © 2008 IEEE.
Picolli, L., Rossini, A., Malcovati, P., Maloberti, F., Borghetti, F., Baschirotto, A. (2008). A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-Triggered Sensors. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 43(2), 312-320 [10.1109/JSSC.2007.914249].
A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-Triggered Sensors
BASCHIROTTO, ANDREA
2008
Abstract
In this paper, a novel 10-bit A/D converter based on a pipeline-like architecture specific for low-noise, self-triggered sensors, (e.g., X-rays and γ-rays spectrometry) is presented. The main innovative feature of the proposed A/D structure is the concept that, for a sampled input signal, a pipeline ADC may behave as a combinatorial logic and may operate without any timing signal (clock). The conversion is obtained asynchronously propagating the partial conversions and the residues through the various stages. This concept is validated by means of a prototype ADC fabricated in a standard 0.35 μm CMOS technology. The active area is 2.24mm2, and it provides a conversion in 2.5 μs (i.e., it can operate with a 400 kS/s data rate) featuring an ENOB equal to 8.91. © 2008 IEEE.
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