Physic researches and discoveries depend heavily from efficient and reliability of the High-Energy Physics (HEP) experiments. The main goal is to study the fundamental constituents of the matter in terms of elementary charge particles, their interactions and their secondary products. The Large Hadron Collider (LHC) at the CERN works every day to discover details on new charged particles as neutrinos and Higgs Bosons. Charges are generated and accelerated from beam collisions inside the LHC. Different detectors are organized in shell structures and are designed to detect few particles topology. Typically, the parameters useful to identify a charged particle are momentum, electrical charge, energy, time of flight and distance. Detectors design is important but it is enhanced from proper electronic readout systems. In the last years, electronics parts are more and more efficient and compact. CMOS integrated solution are preferred to discrete one allowing major reliability, cost reduction and performance improvement. The design is not trivial but not impossible. Some characteristics depend on the electronic designer and his capability to manage the external parasitic effects, as the parasitic capacitance of the connected detector. Unfortunately, phenomena as radiation effects on electronics must be taken in account but they are not completely eliminated. CMOS technology influences strongly the integrated circuit performance and radiation hardness. In this scenario, 3 readout frontend circuits for HEP experiments have been designed, integrated and measured. 2 of them represent 2 different prototypes realized in IBM 130nm technology for ATLAS experiment at CERN laboratory with Max-Plank Institute for Physics collaboration. They include an analog chain in cascade with a digital one. Input charges (up to 100fC) are detected and converted into voltage signals. Their amplitude are proportional to the input and are sent to the following digital part. The digital part provides information about arrival time and amount of the input charge. When the discriminator switches, an event is detected and the Wilkinson ADC starts the voltage-to-time conversion. The full chips have a JTAG section to manage all programmable parameters (i.e. thresholds, hysteresis, deadtime, etc.) The second prototype is designed improving the previous version in terms of supply rejection noise, deadtime range and hysteresis management. The third circuit presented in this thesis is the first readout frontend for Pixel detectors in 28nm technology. The channel includes a charge sensitive preamplifier with an inverter switched based comparator. Reduced supply voltage and 28nm technology imply some difficult in the design with a major tolerance to the radiations, a lower area occupancy and a lower power consumption. The circuits are been designed for 2 different scenarios in terms of detector parasitic capacitance, detectable input charges, supply voltage, threshold voltage, power consumption and noise. In overall cases, the integrated systems provide information about amount of detected input charge and arrival time within 25ns. This aspect is very important and allows avoiding mistakes. Successive collisions lead to spurious signals presence and a single detection could have information about two different events. Maintaining the processing time within 25ns, consecutive collisions are detected as different events. This work is organized as follows. Part I includes a brief summary of the entire work in order to fix the goals of my activities. Then, the Part II is dedicated on a simplified description of the application field and the next target of the future experiments. In particular, some details on the effects induced by the radiation to integrated electronic component are provided. Part III and Part IV represent the core, including 3 readout frontend circuits design and measurements. Finally, there are correlated publications and conclusions.

Le ricerche e le scoperte fatte nell'ambito della fisica sono fortemente dipendenti dall'efficienza e dall'affidabilità degli esperimenti ad alta energia. L'obiettivo principale è lo studio delle particelle che costituiscono la materia in termini di cariche elementari, loro interazioni e prodotti secondari che ne possono derivare. L'LHC (Large Hadron Collider) lavora al CERN ogni giorno con l’obiettivo di scoprire nuovi dettagli su particelle cariche come neutroni e Bosoni di Higgs. Queste sono generate e accelerate all’interno dell’LHC e vengono rilevate da opportuni detector organizzati in una struttura a shell. In questo modo, è possibile avere una caratterizzazione in termini di momento, carica elettrica, energia, tempo di volo e distanza associati alla particella rilevata. La progettazione dei rilevatori è importante come anche quella dell’elettronica vicina. Un grande esperimento richiede un duro lavoro di scienziati e ingegneri. Negli ultimi anni, l’elettronica è sempre più efficiente e compatta grazie alla sostituzione dei componenti discreti con circuiti integrati CMOS. La progettazione deve essere però fatta considerando sia le reti di interfacciamento con i sensori sia l’ambiente radiattivo circostante. Le radiazioni, infatti, possono modificare parzialmente o totalmente le performance e la scelta della tecnologia scalata può però essere di grande aiuto. In questo scenario, sono stati progettati, integrati e misurati 3 circuiti di lettura per esperimenti di fisica delle alte energie. 2 prototipi sono stati realizzati in tecnologia 130nm per l'esperimento ATLAS in collaborazione dell’Istituto Max-Plank di Monaco. Questi prototipi sono pensati per rilevare cariche fino a 100fC e convertirle in un segnale di tensione di ampiezza variabile che sarà processato in digitale per avere informazioni sull’istante di arrivo della carica e sulla sua intensità. A tal fine, gli integrati hanno uno stadio di discriminazione ed un Wilkinson ADC in grado di convertire in un tempo il segnale in tensione ricevuto. Il secondo prototipo è molto simile al primo. Esso è stato migliorato principalmente per poter essere più immune ai disturbi provenienti da masse e alimentazioni. Il terzo circuito presentato in questa tesi è un sistema di lettura progettato per Pixel detectors in tecnologia CMOS 28nm. Il canale integrato include un preamplificatore di carica con un comparatore in cascata. L'utilizzo della tecnologia 28nm con la sua ridotta alimentazione comporta una serie di difficoltà nella progettazione ma anche una maggiore resistenza alle radiazioni, consumi ridotti e una minor area occupata. I circuiti sono stati progettati per due differenti scenari in termini di capacità parassita del rilevatore, cariche di ingresso rilevabili, alimentazioni, soglie, consumi di potenza e rumore. In tutti i casi, però, i sistemi sono in grado di fornire le informazioni sulla carica rilevata in tempi relativamente rapidi (entro 25ns). Questo aspetto è molto importante e permette di evitare errori. Collisioni successive potrebbe causare segnali spuri e si potrebbe rilevare come unico evento due eventi distinti e consecutivi. Questo lavoro è organizzato come segue. La Parte I include una breve introduzione sull'intera attività svolta nei tre anni di attività di ricerca. La Parte II è dedicata alla descrizione semplificata del campo di applicazione ed ai target previsti per i prossimi esperimenti di fisica. In particolare, sono forniti alcuni dettagli su come l'elettronica può essere influenzata dalla presenza delle radiazioni. Le parti III e IV rappresentano il core della tesi perché mirano all'analisi dettagliata dei circuiti progettati e descritti precedentemente in maniera generica. L'analisi prevede una caratterizzazione completa degli integrati con simulazioni e misure. Infine, prima di concludere, la Parte V è dedicata alla pubblicazioni correlate all'attività di ricerca.

(2017). Integrated Read-out Front-end for High-Energy Physics Experiments. (Tesi di dottorato, Università degli Studi di Milano-Bicocca, 2017).

Integrated Read-out Front-end for High-Energy Physics Experiments

RESTA, FEDERICA
2017

Abstract

Physic researches and discoveries depend heavily from efficient and reliability of the High-Energy Physics (HEP) experiments. The main goal is to study the fundamental constituents of the matter in terms of elementary charge particles, their interactions and their secondary products. The Large Hadron Collider (LHC) at the CERN works every day to discover details on new charged particles as neutrinos and Higgs Bosons. Charges are generated and accelerated from beam collisions inside the LHC. Different detectors are organized in shell structures and are designed to detect few particles topology. Typically, the parameters useful to identify a charged particle are momentum, electrical charge, energy, time of flight and distance. Detectors design is important but it is enhanced from proper electronic readout systems. In the last years, electronics parts are more and more efficient and compact. CMOS integrated solution are preferred to discrete one allowing major reliability, cost reduction and performance improvement. The design is not trivial but not impossible. Some characteristics depend on the electronic designer and his capability to manage the external parasitic effects, as the parasitic capacitance of the connected detector. Unfortunately, phenomena as radiation effects on electronics must be taken in account but they are not completely eliminated. CMOS technology influences strongly the integrated circuit performance and radiation hardness. In this scenario, 3 readout frontend circuits for HEP experiments have been designed, integrated and measured. 2 of them represent 2 different prototypes realized in IBM 130nm technology for ATLAS experiment at CERN laboratory with Max-Plank Institute for Physics collaboration. They include an analog chain in cascade with a digital one. Input charges (up to 100fC) are detected and converted into voltage signals. Their amplitude are proportional to the input and are sent to the following digital part. The digital part provides information about arrival time and amount of the input charge. When the discriminator switches, an event is detected and the Wilkinson ADC starts the voltage-to-time conversion. The full chips have a JTAG section to manage all programmable parameters (i.e. thresholds, hysteresis, deadtime, etc.) The second prototype is designed improving the previous version in terms of supply rejection noise, deadtime range and hysteresis management. The third circuit presented in this thesis is the first readout frontend for Pixel detectors in 28nm technology. The channel includes a charge sensitive preamplifier with an inverter switched based comparator. Reduced supply voltage and 28nm technology imply some difficult in the design with a major tolerance to the radiations, a lower area occupancy and a lower power consumption. The circuits are been designed for 2 different scenarios in terms of detector parasitic capacitance, detectable input charges, supply voltage, threshold voltage, power consumption and noise. In overall cases, the integrated systems provide information about amount of detected input charge and arrival time within 25ns. This aspect is very important and allows avoiding mistakes. Successive collisions lead to spurious signals presence and a single detection could have information about two different events. Maintaining the processing time within 25ns, consecutive collisions are detected as different events. This work is organized as follows. Part I includes a brief summary of the entire work in order to fix the goals of my activities. Then, the Part II is dedicated on a simplified description of the application field and the next target of the future experiments. In particular, some details on the effects induced by the radiation to integrated electronic component are provided. Part III and Part IV represent the core, including 3 readout frontend circuits design and measurements. Finally, there are correlated publications and conclusions.
GERVASI, MASSIMO
BASCHIROTTO, ANDREA
readout; radiation; hardness; CMOS; Technologies
readout; radiation; hardness; CMOS; Technologies
FIS/01 - FISICA SPERIMENTALE
English
19-apr-2017
FISICA E ASTRONOMIA - 86R
29
2015/2016
open
(2017). Integrated Read-out Front-end for High-Energy Physics Experiments. (Tesi di dottorato, Università degli Studi di Milano-Bicocca, 2017).
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/158121
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