Mixed-signal speech processing system has been used in microphone-embedded portable electronics. Speech codec is the core of such a system. In speech codecs, sigma-delta modulator is one key block which converts analog voice signal into pulse density modulation (PDM) output for further digital signal processing. This paper shows the design of a triple-mode switched-capacitor sigma-delta modulator for speech codec. High mode (20 kHz signal bandwidth), low mode (4 kHz signal bandwidth), and sleep mode are implemented by addressing a flexible operation current. In order to realize a fully integrated solution, power management circuits dedicated to the modulator are also implemented, which includes frequency detector, LDO, bandgap and reference voltage buffers. The ASIC is fabricated in a 0.18-um CMOS process. In high mode measurement, an A-weighted signal-to-noise ratio (SNR) of 78 dB with -2.5 dBFS input is achieved under 138 uA. In low mode measurement, an SNR of 78 dB with -2 dBFS is achieved under 100 uA. In the standby condition, a sleep mode with current less than 10 uA is realized, so that the battery life is extended.
Zou, L., De Blasi, M., Rocca, G., Grassi, M., Malcovati, P., Baschirotto, A. (2016). Fully integrated triple-mode sigma-delta modulator for speech codec. In NORCAS 2016 - 2nd IEEE NORCAS Conference (pp.1-4). Institute of Electrical and Electronics Engineers Inc. [10.1109/NORCHIP.2016.7792889].
Fully integrated triple-mode sigma-delta modulator for speech codec
BASCHIROTTO, ANDREAUltimo
2016
Abstract
Mixed-signal speech processing system has been used in microphone-embedded portable electronics. Speech codec is the core of such a system. In speech codecs, sigma-delta modulator is one key block which converts analog voice signal into pulse density modulation (PDM) output for further digital signal processing. This paper shows the design of a triple-mode switched-capacitor sigma-delta modulator for speech codec. High mode (20 kHz signal bandwidth), low mode (4 kHz signal bandwidth), and sleep mode are implemented by addressing a flexible operation current. In order to realize a fully integrated solution, power management circuits dedicated to the modulator are also implemented, which includes frequency detector, LDO, bandgap and reference voltage buffers. The ASIC is fabricated in a 0.18-um CMOS process. In high mode measurement, an A-weighted signal-to-noise ratio (SNR) of 78 dB with -2.5 dBFS input is achieved under 138 uA. In low mode measurement, an SNR of 78 dB with -2 dBFS is achieved under 100 uA. In the standby condition, a sleep mode with current less than 10 uA is realized, so that the battery life is extended.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.