In this paper we describe a Content Addressable Memory architecture designed in 28 nm CMOS technology and based on the 65 nm XORAM cell previously developed. The cell is composed by two main blocks: a 6T SRAM, and a 4T XOR logic gate. Each XORAM cell makes a bitwise comparison between input data and stored data. The memory is organized in 18-bit words, and all the 18 XOR outputs bits must have a low logic value to trigger a high logic value of the single bit match line. A 18-input NOR gate performs this operation. The memory operation is triggered by the change of the least significant bit of the 18-bit input word, which is delayed w.r.t. The other bits. In this way, the logic does not require any clock. The proposed architecture is based on CMOS combinational logic, and it does not require any precharge operation, nor control and timing logic. The Associative Memory block is useful for several pattern recognition tasks, such as track recognition in high energy physics experiments, and image recognition for medical applications.

Annovi, A., Baschirotto, A., Beretta, M., Biesuz, N., Citraro, S., Crescioli, F., et al. (2016). A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (pp.392-395). Institute of Electrical and Electronics Engineers Inc. [10.1109/ICECS.2015.7440331].

A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications

BASCHIROTTO, ANDREA
Secondo
;
DE MATTEIS, MARCELLO;FARY, FEDERICO;PEZZOTTA, ALESSANDRO;
2016

Abstract

In this paper we describe a Content Addressable Memory architecture designed in 28 nm CMOS technology and based on the 65 nm XORAM cell previously developed. The cell is composed by two main blocks: a 6T SRAM, and a 4T XOR logic gate. Each XORAM cell makes a bitwise comparison between input data and stored data. The memory is organized in 18-bit words, and all the 18 XOR outputs bits must have a low logic value to trigger a high logic value of the single bit match line. A 18-input NOR gate performs this operation. The memory operation is triggered by the change of the least significant bit of the 18-bit input word, which is delayed w.r.t. The other bits. In this way, the logic does not require any clock. The proposed architecture is based on CMOS combinational logic, and it does not require any precharge operation, nor control and timing logic. The Associative Memory block is useful for several pattern recognition tasks, such as track recognition in high energy physics experiments, and image recognition for medical applications.
slide + paper
Associative processing; Associative storage; CMOS integrated circuits; High energy physics; Image recognition; Logic gates; Medical applications; Medical imaging; Memory architecture; Pattern recognition; Reconfigurable hardware; Static random access storage; Associative memory; Combinational logic; High energy physics experiments; Least significant bits; Memory operations; Proposed architectures; Track recognition; XOR logic gates; Computer circuits
English
IEEE International Conference on Electronics, Circuits, and Systems (ICECS), December 06-09
2015
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
9781509002467
2016
2016-
392
395
7440331
none
Annovi, A., Baschirotto, A., Beretta, M., Biesuz, N., Citraro, S., Crescioli, F., et al. (2016). A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (pp.392-395). Institute of Electrical and Electronics Engineers Inc. [10.1109/ICECS.2015.7440331].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10281/123750
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